1. Field of the Invention
The invention relates to a semiconductor device including a low-voltage circuit, which constitutes a high-speed microcomputer and a high-speed logic circuit, for instance, and a high-voltage circuit both formed on a common semiconductor substrate, and further to a method of fabricating the same.
2. Description of the Related Art
A logic circuit for a micro-computer and so on is operated generally with a low-voltage power supply providing a voltage of 7V or smaller, and processes signals having a voltage of 7V or smaller. Accordingly, a microcomputer is requested to have a structure capable of being operated at a voltage such as 7V or smaller. On the other hand, a high-voltage circuit deals with a voltage much greater than 7V, and hence is requested to have a structure capable of being operated at a high voltage.
FIGS. 1A to 1D are cross-sectional views of low-voltage MOS transistors and high-voltage MOS transistors both used in a microcomputer. FIGS. 1A to 1D illustrate a high-voltage NMOS transistor, a high-voltage PMOS transistor, a low-voltage NMOS transistor, and a low-voltage PMOS transistor, respectively.
As illustrated in FIGS. 1A and 1B, the high-voltage NMOS and PMOS transistors are formed with a high-voltage nxe2x88x92-type well 2 in a pxe2x88x92-type semiconductor substrate 1. The high-voltage NMOS transistor illustrated in FIG. 1A is further formed with a pxe2x88x92-type channel formation region 3 in the nxe2x88x92-type well region 2, whereas the high-voltage PMOS transistor illustrated in FIG. 1B is further formed with a pxe2x88x92-type extended drain region 4 in the nxe2x88x92-type well region 2. Thus, the high-voltage NMOS and PMOS transistors are characterized by that drain electrodes of them have a highly doped n- or p-type region 5 serving as a drain diffusion layer, surrounded by the regions 2 and 4 doped more lightly than 5 sources 6. The more lightly doped regions 2 and 4 than the sources 6 ensure that the high-voltage NMOS and PMOS transistors operate at a high voltage.
On the other hand, as is obvious in view of FIGS. 1C and 1D, low-voltage NMOS and PMOS transistors are not formed with regions corresponding to the above-mentioned regions 2 and 4 more lightly doped than the sources 6.
Hence, if a semiconductor device including high-voltage and low-voltage MOS transistors is to be fabricated in order to drive a fluorescent character display tube or a liquid crystal character display tube with a micro-computer, for instance, there are two ways for fabrication such a semiconductor device.
The first one is to fabricate a low-voltage MOS transistor used for a microcomputer and a high-voltage MOS transistor as a driver on different semiconductor substrates, and use them as two LSI chips. The second one is to fabricate a single LSI chip having a semiconductor substrate on which high-voltage and low-voltage MOS transistors are formed together. Comparing those two ways, the second one where a single LSI chip is fabricated is more advantageous than the first one with respect to a size of a device and fabrication cost.
FIGS. 2A to 2L are cross-sectional views of a semiconductor device, illustrating respective steps, in order, of a conventional method of fabricating a semiconductor device including a logic circuit and a high-voltage circuit on a common semiconductor substrate. In this example explained hereinbelow, a low-voltage NMOS transistor, a low-voltage PMOS transistor, a high-voltage NMOS transistor, and a high-voltage PMOS transistor are all to be fabricated on a common p-type silicon substrate. First, there is prepared a p-type silicon substrate 401 having an impurity concentration in the range of 0.5xc3x971016 to 1xc3x971016 cmxe2x88x923. Then, as illustrated in FIG. 2A, an oxide film 402 is grown by a thickness of 480 nm on the p-type silicon substrate 401, followed by deposition a photoresist film 403 all over the oxide film 402. Then, a first photolithography and etching step is carried out to thereby partially remove the oxide film 402 in regions where high-voltage and low-voltage n-type well regions are to be formed, with the photoresist film 403 being used as an etching mask.
Then, as illustrated in FIG. 2B, after the photoresist film 403 has been removed, a thin oxide film 491 is grown on a surface of the p-type silicon substrate 401 in exposed regions thereof. The oxide film 491 has a thickness of about 40 nm. The oxide film 491 is grown for preventing channeling in ion-implantation and precipitation of impurities caused by thermal annealing carried out at a high temperature. Then, the p-type silicon substrate 1 is implanted at 150 KeV with doses of 1xc3x971013 cmxe2x88x922 of n-type impurity ions such as phosphorus with the oxide film 402 being used as an ion-implantation mask. Thus, there are formed ionimplanted regions 404A, 404B and 404D.
Then, a first annealing is carried out at 1200xc2x0 C. for about 5 hours. As a result, the ion-implanted regions or n-type impurity regions 404A, 404B and 404D are diffused laterally and in a depth-wise direction of the p-type silicon substrate 401 to thereby make impurity regions 405A, 405B and 405D, as illustrated in FIG. 2C. The oxide film 491 is all removed, and then a thin oxide film 492 is formed again at a surface of the p-type silicon substrate 401.
Then, a photoresist film 403 is formed again entirely over the oxide film 492. Then, a second lithography step is carried out to the photoresist film 403 employing an alignment mark having been formed in the first lithography step, to thereby pattern the photoresist film 403 into a desired pattern. Then, p-type impurities are ion-implanted into the n-type well region 405B in a selected area with the patterned photoresist film 403 being used as a mask, to thereby form an impurity region 406B in the n-type well region 405B, as illustrated in FIG. 2D. The thus formed impurity region 406 will make a high-voltage p-type well for the high-voltage PMOS transistor.
Then, as illustrated in FIG. 2E, a nitride film 407 is grown on the oxide film 492 by a thickness in the range of 150 nm to 240 nm, for instance. Then, a photoresist film 403 is deposited all over the nitride film 407, followed by a third photolithography step to thereby pattern the photoresist film 403. Then, the nitride film 407 is etched for removal in selected regions where device isolation regions are to be formed, with the patterned photo film 403 being used as a mask. After removal of all the photoresist film 403, the product is oxidized at 1000xc2x0 C. to 1200xc2x0 C. for about 3 hours. This oxidation doubles as a second annealing.
As a result, as illustrated in FIG. 2F, device isolation oxide films 410 are formed at a surface of the p-type silicon substrate 410. The oxide films 410 have a thickness in the range of about 50 nm to about 70 nm. By the above-mentioned oxidation, the n-type impurity regions 405A, 405B and 405D, and the p-type impurity region 406B are diffused laterally and in a depth-wise direction of the silicon substrate 401 to thereby make n-type impurity regions 408A, 408B and 408D, and the p-type impurity region 409B, respectively.
The steps mentioned so far are a known method called LOCOS for defining device formation regions. LOPOS or trench type LOCOS may be substituted for LOCOS, in which case, a distance Xn2 (see FIG. 2F) between the oxide film 410 and an outer boundary of the n-type impurity region 408A varies in dependence on a target breakdown voltage of the high-voltage NMOS transistor, and further a distance Xp2 (see FIG. 2E) between the oxide film 410 and an outer boundary of the p-type impurity region 409B varies in dependence on a target breakdown voltage of the high-voltage PMOS transistor. The distances Xn2 and Xp2 are dependent on the first and second annealing, and hence the first and second annealing are carried out in a certain range of a temperature and a period of time.
Then, as illustrated in FIG. 2G, after the nitride film 407 and the oxide film 492 have been removed, an oxide film 411 which will make a dielectric, insulating film of MOS transistors is grown at a surface of the p-type silicon substrate 401.
Then, a photoresist film 403 is deposited entirely over the product, and patterned into a desired pattern in a fourth photolithography step. Then, the dielectric, insulating film 411 is removed in a selected region where the low-voltage MOS transitors are to be formed, with the patterned photoresist film 403 being used as a mask, as illustrated in FIG. 2H.
Then, after removal of the photoresist film 403, an oxide film or a dielectric, insulating film 412 for the low-voltage MOS transistors is grown at a surface of the silicon substrate, as illustrated in FIG. 2I. The oxide film or dielectric, insulating film 411 for the high-voltage MOS transistors is concurrently grown into an insulating film 413.
Then, as illustrated in FIG. 2J, a film 414 which will make gate electrodes of MOS transistors is grown all over the product. The film 414 is made of polysilicon or a multi-layered structure of polysilicon and metal silicide.
Then, a photoresist film (not illustrated) is deposited all over the polysilicon film 414, and then is patterned into a desired pattern by a fifth photolithography. Then, as illustrated in FIG. 2K, the polysilicon film 414 is etched in selected regions with the patterned photoresist film being used as an etching mask. As a result, there are formed gate electrodes 414C, 414D, 414A and 414B of the low-voltage NMOS transistor, the low-voltage PMOS transistor, the high-voltage NMOS transistor and the high-voltage PMOS transistor, respectively.
Then, as illustrated in FIG. 2L, there are formed source diffusion layers 421, 424 and drain diffusion layers 422, 425 of the low-voltage NMOS transistor and the high-voltage NMOS transistor, and channel well diffusion layers 423 and 426 of the low-voltage PMOS transistor and the high-voltage PMOS transistor. Those layers 421, 424, 422, 425, 423 and 426 are formed of highly doped n-type impurity regions. Similarly, there are formed source electrodes 432, 435 and drain electrodes 433, 436 of the low-voltage PMOS transistor and the high-voltage PMOS transistor, and channel well electrodes 431 and 434 of the low-voltage NMOS transistor and the high-voltage NMOS transistor. Those layers 432, 435, 433, 436, 431 and 434 are formed of highly doped p-type impurity regions. Thereafter, the thus formed drain, source, gate and channel well electrodes are electrically connected with each other through metal wiring layers in a conventional manner to thereby complete LSI.
In accordance with the above-mentioned conventional method, since the highly doped impurity regions constituting the drain electrodes 425 and 436 of the high-voltage MOS transistors are surrounded by the lightly doped impurity regions 408A and 409B, additional steps have to be carried out in comparison with a method of fabricating a low-voltage MOS transistor. That is, a step of annealing in the range of 1000xc2x0 C. to 1200xc2x0 C. has to be additionally carried out twice, and further a photolithography step for forming impurity regions in selected areas has to be additionally carried out twice. By adding those steps to steps of fabricating a low-voltage MOS transistor, the number of fabrication steps for fabricating a semiconductor device is increased, resulting in a longer period of time for fabrication of a semiconductor device.
It is known that parameters for determining a breakdown voltage, the most important characteristic of a high-voltage MOS transistor, are concentrations of impurities in both an extended drain region and a channel region, and a distance between an outer end of an extended drain region and a device isolation layer, that is, distances Xn1 and Xp1 as illustrated in FIGS. 1A and 1B.
FIGS. 3A and 3B show the relation between the above-mentioned parameters and a breakdown voltage. The impurity concentration is dependent on both an amount of impurities and a time of annealing at a high temperature (generally, a few hours to about 10 hours at 1000xc2x0 C. to 1200xc2x0 C.). In the conventional method, since high temperature thermal annealing is carried out a lot of times, it is quite difficult to control the impurity concentration with high accuracy.
The above-mentioned distances Xn1 and Xp1 correspond to distances Xn3 and Xp3 illustrated in FIG. 2L. The distance Xn3 in the high-voltage NMOS transistor is determined in a complicated manner. That is, the distance Xn3 is dependent on the lateral diffusion of the region 404A, into which n-type impurities have been implanted in FIG. 2B, caused by two high temperature thermal annealing. The distance Xp3 in the high-voltage PMOS transistor is determined in a more complicated manner. The region 406B having been formed by implanting p-type impurities thereinto with the oxide film 402 being used as an alignment mark is laterally diffused by the first high temperature annealing to thereby make the high-voltage p-type well region 409B illustrated in FIG. 2L. Apart from the high-voltage p-type well region 409B, the device isolation oxide film 410 is formed also with the oxide film 402 being used as an alignment mark. Namely, the distance Xp2 between the device isolation oxide film 410 and an outer end of the high-voltage p-type well region 409B is formed under the influence of both a dispersion caused by two photolithography steps and a dispersion caused by a high temperature thermal annealing step. Hence, there is generated a dispersion in a breakdown voltage of both the high-voltage NMOS and PMOS transistors.
When an electronic circuit is to be formed of MOS transistors, designability of a circuit may be enhanced, if a channel region of MOS transistors is electrically independent from a semiconductor substrate. For instance, in a circuit which employs NMOS transistor, and is called a negative power-supply circuit because it deals with a voltage lower than a voltage of a semiconductor substrate, a channel region of MOS transistor has to be electrically isolated from a semiconductor substrate.
However, in the above-mentioned conventional method of fabricating a semiconductor device, the channel region of the high-voltage PMOS transistor is electrically isolated from the silicon substrate, but the channel region of the high-voltage NMOS transistor is kept at the same voltage as that of the silicon substrate, which restricts the designability of a semiconductor device.
Japanese Patent Publication No. 2510751 (Japanese Unexamined Patent Publication No. 2-284462 published on Nov. 21, 1990) based on U.S. patent application Ser. No. 324,869 filed on Mar. 17, 1989 by Delco Electronics Corporation has suggested a method of fabricating -voltage and low-voltage CMOS transistors on a common integrated circuit chip. In accordance with the suggested method, an extended drain well region having a first conductivity, of a high-voltage transistor having a first conductivity is formed concurrently with well regions having a first conductivity, of high-voltage and low-voltage transistors having a second conductivity, and an extended drain well region having a second conductivity, of a high-voltage transistor having a second conductivity is formed by ion-implantation separate from the above-mentioned well region having a first conductivity.
Japanese Unexamined Patent Publication No. 7-307394 based on U.S. patent application Ser. No. 224,948 filed on Apr. 8, 1994 by Texas Instrument Incorporated has suggested an extended drain resurf lateral DMOS device. In accordance with the suggested method, there is provided a method of readily fabricating an integrated circuit including a high-voltage PMOS device and/or high-voltage NMOS device, and a low-voltage PMOS device and/or low-voltage NMOS device.
It is an object of the present invention to provide a semiconductor device in which low-voltage and high-voltage MOS transistors can be fabricated on a common semiconductor substrate in the smallest number of fabrication steps. It is also an object of the present invention to provide a method of fabricating the above-mentioned semiconductor device.
Another object of the present invention is to provide a semiconductor device in which both an electrically conductive region serving as a channel region of high-voltage NMOS transistor and an electrically conductive region serving as a channel region of high-voltage PMOS transistor are electrically independent from a semiconductor substrate. It is also another object of the present invention to provide a method of fabricating the above-mentioned semiconductor device.
A further object of the present invention is to provide a semiconductor device in which a distance between an extended drain region and a device isolation region can be controlled with high accuracy, and also provide a method of fabricating the same.
In one aspect of the present invention, there is provided a semiconductor device including (a) a semiconductor substrate having a first conductivity, (b) a first, low-voltage MOS transistor formed on the semiconductor substrate, (c) a second, high-voltage MOS transistor formed on the semiconductor substrate and having a first conductivity, (d) a third, high-voltage MOS transistor formed on the semiconductor substrate and having a second conductivity, both a first electrically conductive region containing a channel region of the third MOS transistor and a second electrically conductive region containing an extended drain region of the second MOS transistor being electrically independent of the semiconductor substrate.
It is preferable that the channel region and the extended drain region have a common conductivity, and that the channel region and the extended drain region have the same conductivity as that of the semiconductor substrate. It is preferable that the channel region and the extended drain region are both surrounded by well regions having a second conductivity. It is preferable that an insulating film formed below gate electrodes of the second and third MOS transistors at least partially has the same thickness as that of an insulating film formed below a gate electrode of the first MOS transistor.
In another aspect of the present invention, there is provided a method of fabricating a semiconductor device, including the steps, in order, of (a) forming first well regions in a semiconductor substrate in all regions in which high-voltage and low-voltage MOS transistors are to be formed, the semiconductor substrate having a first conductivity and the first well regions having a second conductivity, (b) forming an isolation layer on the semiconductor substrate for isolating the first well regions from each other, (c) forming high-voltage well regions having a first conductivity and low-voltage well regions one of which has a first conductivity and another of which has a second conductivity, and (d) forming MOS transistors on the high-voltage and low-voltage well regions.
There is further provided a method of fabricating a semiconductor device, including the steps, in order, of (a) forming an isolation layer at a surface of a semiconductor substrate for isolating device formation regions from each other, the semiconductor substrate having a first conductivity, (b) forming first well regions in the semiconductor substrate in all regions in which high-voltage and low-voltage MOS transistors are to be formed, the first well regions having a second conductivity, (c) forming high-voltage well regions having a first conductivity and low-voltage well regions one of which has a first conductivity and another of which has a second conductivity, and (d) forming MOS transistors on the high-voltage and low-voltage well regions.
It is preferable that the high-voltage and low-voltage well regions are formed with the isolation layer being used as a mark. For instance, the high-voltage well regions and the low-voltage well region having a first conductivity are first formed, and then the low-voltage well region having a second conductivity is formed in the step (c). The step (d) of forming MOS transistors on the well regions may include the steps of forming insulating films and gate electrodes for each of the MOS transistors, forming highly impurity-doped regions having a second conductivity, the highly impurity-doped regions serving as source and drain electrodes of NMOS transistors, and forming highly impurity-doped regions having a first conductivity, the highly impurity-doped regions serving as source and drain electrodes of PMOS transistors.
For instance, the high-voltage and low-voltage well regions may be formed by ion-implantation into the semiconductor substrate through an insulating layer formed on a surface of the semiconductor substrate. It is parable that annealing at 1000xc2x0 C. or greater is all carried out before the high-voltage well regions are formed. Namely, it is preferable that annealing at 1000xc2x0C. or greater is not carried out after the high-voltage wells having a first conductivity have been formed.
It is preferable that the high-voltage well regions are concurrently formed, and wherein one of the high-voltage well regions serves as an extended drain region of the high-voltage MOS transistor having a first conductivity, and the other of the high-voltage well regions serves as a channel region of the high-voltage MOS transistor having a second conductivity.
In accordance with the present invention, since high-voltage and low-voltage NMOS and PMOS transistors are formed within high-voltage well regions having a conductivity opposite to a conductivity of a semiconductor substrate, all MOS transistors are electrically independent from the semiconductor substrate, ensuring designability of this kind of semiconductor device.
In the method in accordance with the present invention, after high-voltage well regions of all MOS transistors and a device isolation layer have been formed, there are formed extended drain regions, channel regions, and low-voltage well regions. Thereafter, MOS transistors are formed. Hence, it is possible to fabricate a semiconductor device only by adding the smallest number of fabrication steps to the conventional steps of fabricating low-voltage MOS transistor. This ensures simplification in fabrication steps.
In accordance with the present invention, it is possible to form a channel region and an extended drain region of high-voltage MOS transistors with a device isolation layer being used as a reference mark. In addition, since a high temperature thermal annealing is not carried out after ion-implantation of impurities into a semiconductor substrate for forming the channel region and the extended drain region, it would be possible to control, with high accuracy, a distance between the channel region or extended drain region and the device isolation region both of which are factors for determining a breakdown voltage of high-voltage MOS transistors. Furthermore, it is also possible to fabricate a semiconductor device having a desired breakdown voltage, by controlling a concentration of impurities to be implanted into a substrate for forming the channel region or extended drain region.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.